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    SubjectRe: Memory Barrier Definitions
    On Wed, May 08, 2002 at 10:27:10AM -0500, Dave Engebretsen wrote:
    > I am curious what the definition of memory barriers is for IA64, Sparc,
    > and x86-64.
    >
    > >From what I can tell, sparc and x86-64 are like alpha and map directly
    > to the existing mb, wmb, and rmb semantics, incluing ordering between
    > system memory and I/O space. Is that an accurate assesment?

    I don't think it is true for alpha, but it is true
    for x86-64. x86-64 by default has strong ordering for most loads/stores.
    It is possible to use weak ordering for special marked stores. For that
    there are special read and write and read/write barriers which apply
    to all memory (not distinction between io space and other memory). In
    addition there is a way to mark special memory areas as write combining and
    some other settings, but that is ordered by the normal barriers too.

    -Andi

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