Messages in this thread | ![/](/images/icornerl.gif) | | Date | Fri, 17 May 2002 13:57:26 -0400 (EDT) | From | Bill Davidsen <> | Subject | Re: Q: x86 interrupt arrival after cli |
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On Thu, 16 May 2002, Richard B. Johnson wrote:
> <--- HIGHEST ------------------- LOWEST ----> > > IRQ0, 1, 8, 9, 10, 11, 12, 13, 14, 15, 3, 4, 5, 6, 7 > | | | | | | | |_ printer > | | | | | | |____ Floppy > | | | | | |_______ Fixed disk > | | | | |__________ Serial 0 > | | | |_____________ Serial 1 > | | | > | | |___________ IRQ2->IRQ8 cascade RTC > | |______________ Keyboard > |_________________ PIT channel 0 > > IFF the IO-APIC is programmed to emulate the old dual controllers.
Yes, and if anyone missed this subtle point, the priorities are programmable! There have been patches, particularly back in 2.1.120+, to diddle priority to make marginal system work, or move the failures to something with more robust retries.
Nice diagram, I'm taking it to a meeting (credited to you of course) where I will be talking about interrupt use on parallel ports.
-- bill davidsen <davidsen@tmr.com> CTO, TMR Associates, Inc Doing interesting things with little computers since 1979.
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