Messages in this thread | | | Date | Thu, 18 Apr 2002 12:04:35 -0400 (EDT) | From | Bill Davidsen <> | Subject | Re: SMP P4 APIC/interrupt balancing |
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On Wed, 17 Apr 2002, James Bourne wrote:
> After Ingo forwarded me his original patch (I found his patch via a web > based medium, which had converted all of the left shifts to compares, and > now I'm very glad it didn't boot...) and the system is booted and is > balancing most of the interrupts at least. Here's the current output > of /proc/interrupts
Is this positive or negative on performance? If you have a system getting so many interrupts that one CPU can't handle them, obviously there is a gain. However, by thrashing the cache of all CPUs instead of just one you have some memory performance cost.
I first looked at this for a mainframe vendor who decided that putting all the interrupts in one CPU was better. That was then, this is now, but I am curious about metrics, like real and system time doing a kernel compile, etc.
-- bill davidsen <davidsen@tmr.com> CTO, TMR Associates, Inc Doing interesting things with little computers since 1979.
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