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    SubjectRe: [Lse-tech] Re: 10.31 second kernel compile
    On Sat, Mar 16, 2002 at 09:05:04PM +0100, Andi Kleen wrote:
    > On Sat, Mar 16, 2002 at 12:57:11PM -0700, wrote:
    > > On Sat, Mar 16, 2002 at 08:32:26PM +0100, Andi Kleen wrote:
    > > > x86-64 aka AMD Hammer does hardware (or more likely microcode) search of
    > > > page tables.
    > > > It has a 4 level page table with 4K pages. Generic Linux MM code only sees
    > > > the first slot in 4th level page limit user space to 512GB with 3 levels.
    > >
    > > What about 2M pages?
    > They are not supported for user space, but used in private mappings
    > for kernel text and direct memory mappings. Generic code never sees them.
    > That will hopefully change eventually because 2M pages are a bit help for
    > a lot of applications that are limited by TLB thrashing, but needs some
    > thinking on how to avoid the fragmentation trap (e.g. I'm considering
    > to add a highmem zone again just for that and use rmap with targetted
    > physical freeing to allocating them)

    To me, once you have a G of memory, wasting a few meg on unused process
    memory seems no big deal.

    > > There was something in some AMD doc about preventing tlbflush on process
    > > switch - through a context like thing perhaps? Any idea?
    > There are global pages which are normally not flushed over context switch.
    > That is used for all kernel mappings.
    > There is also some optimization in the CPU that tries to do a selective
    > flush only when you reload CR3, but as far as I can see doesn't help
    > for the Linux context switch. It only works around broken TLB flushing
    > algorithms in some Windows version.

    They say:
    Hammer microarchitecture features a flush filter allowing multiple
    processes to share TLB without SW intervention.

    Not a lot of technical detail in that.

    > -Andi

    Victor Yodaiken
    Finite State Machine Labs: The RTLinux Company.

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