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SubjectRe: [patch] PIIX rewrite patch, pre-final
Date
From
Let me try and contribute a bit more back to this wonderful document..


> 0x1078 Cyrix
> 0x0102 CX5530 x x x x x - - - x
>
> known bugs:
> - all: busmaster transfers need to be 16 byte aligned instead of wor=
> d
> aligned.

Add: A DMA block of 65536 bytes comes out as 0 bytes in the chipset.

> 0x1166 ServerWorks
> 0x0211 OSB4 x x ? ? x - - - x
> 0x0212 CSB5
> < 0x92 x x ? ? x x - - -
> >=3D 0x92 x x ? ? x x x - -
>
> known bugs:
> - OSB4: at least some chip revisions can't do Ultra DMA mode 1 and a=
> bove

Interesting - any idea which you've found a problem. One errata we see in
the Linux case with specific drive/board combinations is a
transfer completing but the DMA busy bit never being cleared. The next
DMA transaction is shifted by 4 bytes starting with the last dword of
the previous I/O (as if the DMA engine got something stuck in a FIFO)

> - CSB5: no host side cable type detection.
(Except with extra glue - eg on Dell boxes)

Alan
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