Messages in this thread |  | | | Date | Tue, 5 Feb 2002 15:17:58 -0800 (PST) | | From | Joel Jaeggli <> | | Subject | Re: driverfs support for motherboard devices |
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On Tue, 5 Feb 2002, Patrick Mochel wrote:
<really big snip>
> > Case 3: Quad channel DEC Bridge > > Ok, maybe I don't understand completely what you're talking about, Andre. > That's just a 4 channel IDE controller, that happens to be on the board? > So, it's looks the same as the last example. > > Unless, I'm missing something, which is always likely.
actually it's two two channel controllers on one board...
Uniform Multi-Platform E-IDE driver Revision: 6.31 ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx PIIX3: IDE controller on PCI bus 00 dev 39 PIIX3: chipset revision 0 PIIX3: not 100% native mode: will probe irqs later ide0: BM-DMA at 0xffa0-0xffa7, BIOS settings: hda:pio, hdb:pio ide1: BM-DMA at 0xffa8-0xffaf, BIOS settings: hdc:pio, hdd:pio PDC20268: IDE controller on PCI bus 01 dev 10 PDC20268: chipset revision 2 PDC20268: not 100% native mode: will probe irqs later PDC20268: ROM enabled at 0x000dc000 PDC20268: pci-config space interrupt mirror fixed. PDC20268: (U)DMA Burst Bit ENABLED Primary MASTER Mode Secondary MASTER Mode. ide2: BM-DMA at 0xcc00-0xcc07, BIOS settings: hde:pio, hdf:pio ide3: BM-DMA at 0xcc08-0xcc0f, BIOS settings: hdg:pio, hdh:pio PDC20268: IDE controller on PCI bus 01 dev 08 PDC20268: chipset revision 2 PDC20268: not 100% native mode: will probe irqs later PDC20268: ROM enabled at 0xeded0000 PDC20268: pci-config space interrupt mirror fixed. PDC20268: (U)DMA Burst Bit ENABLED Primary MASTER Mode Secondary MASTER Mode. ide4: BM-DMA at 0xb800-0xb807, BIOS settings: hdi:pio, hdj:pio ide5: BM-DMA at 0xb808-0xb80f, BIOS settings: hdk:pio, hdl:pio
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