![]() | |||||||||||||
Messages in this thread |
On Sun, Dec 22, 2002 at 12:47:51PM -0700, Eric W. Biederman wrote: > Not if it is an NMI or an SCI interrupt. The latter on x86 places > the cpu in System Management Mode, and what the cpu does from that > point forward is out of our control.> > Though disabling cpu controlled IRQs help if you are dealing > with any normal IRQs. I meant the timer interrupt in the first place. I assumed it's the only one that does matter on this stage of the boot process. What else could happen (in the real world terms)? > The window needs to be small from the PCI bus perspective, not in cpu > clocks. Write, Read, Write is only something like 9 PCI bus clocks. No, the window is huge from the PCI bus perspective. IIRC, PCI config read/write on x86 works like this (I may be wrong though): i/o port write (BAR address) ~1us i/o port read (BAR value after writing ~0) ~1us i/o port write (BAR address) ~1us i/o port write (saved BAR value) ~1us It's a little bit more than 9 PCI clocks. Am I missing something? Ivan. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ | ||||||||||||
| Last update: 2005-03-22 13:31 [from the cache] ©2003-2008 | |||||||||||||