Messages in this thread | | | Date | Mon, 23 Dec 2002 00:05:42 +0300 | From | Ivan Kokshaysky <> | Subject | Re: PATCH 2.5.x disable BAR when sizing |
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On Sun, Dec 22, 2002 at 12:47:51PM -0700, Eric W. Biederman wrote: > Not if it is an NMI or an SCI interrupt. The latter on x86 places > the cpu in System Management Mode, and what the cpu does from that > point forward is out of our control. > > Though disabling cpu controlled IRQs help if you are dealing > with any normal IRQs.
I meant the timer interrupt in the first place. I assumed it's the only one that does matter on this stage of the boot process. What else could happen (in the real world terms)?
> The window needs to be small from the PCI bus perspective, not in cpu > clocks. Write, Read, Write is only something like 9 PCI bus clocks.
No, the window is huge from the PCI bus perspective. IIRC, PCI config read/write on x86 works like this (I may be wrong though): i/o port write (BAR address) ~1us i/o port read (BAR value after writing ~0) ~1us i/o port write (BAR address) ~1us i/o port write (saved BAR value) ~1us
It's a little bit more than 9 PCI clocks. Am I missing something?
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