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Correct. Please look at Table B-1. Most of MSRs are shared, but some MSRs are unique in each logical processor, to provide the x86 architectural state. Those SYSENTER MSRs, and Machine Check register save state (IA32_MCG_XXX), for example, are unique. Jun > -----Original Message----- > From: Mikael Pettersson [mailto:mikpe@csd.uu.se] > Sent: Sunday, December 22, 2002 4:34 AM > To: mingo@elte.hu; torvalds@transmeta.com > Cc: drepper@redhat.com; Nakajima, Jun; linux-kernel@vger.kernel.org > Subject: Re: Intel P6 vs P7 system call performance > > On Sun, 22 Dec 2002 11:23:08 +0100 (CET), Ingo Molnar wrote: > >while reviewing the sysenter trampoline code i started wondering about > the > >HT case. Dont HT boxes share the MSRs between logical CPUs? This pretty > >much breaks the concept of per-logical-CPU sysenter trampolines. It also > >makes context-switch time sysenter MSR writing impossible, so i really > >hope this is not the case. > > Some MSRs are shared, some aren't. One must always check this in > the IA32 Volume 3 manual. The three SYSENTER MSRs are not shared. > > However, no-one has yet proven that writing to these in the context > switch path has acceptable performance -- remember, there is _no_ > a priori reason to assume _anything_ about performance on P4s, > you really do need to measure things before taking design decisions. > > Manfred had a version with fixed MSR values and the varying data > in memory. Maybe that's actually faster. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ | |||||||||
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