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On Sun, 22 Dec 2002 11:23:08 +0100 (CET), Ingo Molnar wrote: >while reviewing the sysenter trampoline code i started wondering about the >HT case. Dont HT boxes share the MSRs between logical CPUs? This pretty >much breaks the concept of per-logical-CPU sysenter trampolines. It also >makes context-switch time sysenter MSR writing impossible, so i really >hope this is not the case. Some MSRs are shared, some aren't. One must always check this in the IA32 Volume 3 manual. The three SYSENTER MSRs are not shared. However, no-one has yet proven that writing to these in the context switch path has acceptable performance -- remember, there is _no_ a priori reason to assume _anything_ about performance on P4s, you really do need to measure things before taking design decisions. Manfred had a version with fixed MSR values and the varying data in memory. Maybe that's actually faster. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ | |||||||||
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