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    SubjectRe: Athlon/AGP issue update
    >AGP might be non-coherent. If so, then the CPU should use a
    >non-coherent mapping to avoid useless memory bus traffic.
    >User code has access to some cache control instructions,
    >so one may mark the memory cacheable for better performance
    >even when it is non-coherent. ("flush when you're done")

    That's unfortunately not enough. The mapping of the page to
    userland and the in-kernel mapping of the AGP aperture are done
    with non-cacheable attribute. _BUT_, that same memory is also
    mapped as part of the RAM linear mapping of the kernel (the
    BAT mapping on PPC). The problem happens when some code working
    near the end of a different page via this linear mapping cause
    a speculative access to happen on the next page. This will have
    the side-effect of loading the cache with a line from the page
    used by AGP.

    I think PPC does only speculative reads, but even those (non dirty
    cache lines) may cause trouble in our case.

    Now, we have to check if the PPC is allowed to do speculative
    reads accross page boundaries. If it's the case, then we are screwed
    and I will have to cleanup the code allowing the kernel to run without
    the BAT mapping (with a performance impact unfortunately).


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