Messages in this thread | | | Date | Wed, 23 Jan 2002 15:50:59 +0100 (CET) | From | Manfred Spraul <> | Subject | Re: Athlon/AGP issue update |
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On Wed, 23 Jan 2002, David S. Miller wrote:
> > This isn't true. The speculative store won't get data into the > cache if there is a TLB miss. > The Pentium III loads TLB entries speculatively, there is a Intel document how to flush tbl entries where they explicitely mention that.
> 4MB pages map the GART pages and "other stuff", ie. memory used by > other subsystems, user pages and whatever else. This is the only > way the bug can be thus triggered for kernel mappings, which is why > turning off 4MB pages fixes this part. >
We might be luky - pIII performs speculative tlb loads, and Athlon performs spurious cache line writeouts, but I don´t trust such solutions.
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