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    SubjectRe: Encrypted Swap
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    "Richard B. Johnson" <root@chaos.analogic.com> writes:

    > On Fri, 17 Aug 2001, David Christensen wrote:
    >
    > > > > Ryan Mack proclaimed:
    > > Most modern firmware does NOT clear memory during POST, it takes too long.

    Clearing memory on most machines takes a 1s or less. Think of memory
    fill rates at the 800MB/s level. Most BIOS's seem to clear some of
    the memory but I haven't read their code to see what they are doing.

    > > Certain compatibility areas are usually cleared (such as the 1st megabyte)
    > > but the rest is
    > > left as is, except for a few read/writes (usually on a megabyte boundary).
    > > The
    > > exception to this rule is ECC systems. They have to be written to make sure
    > > the
    > > ECC information is correct.
    Correct.

    > > SDRAM memory sizing is usually done by reading an EEPROM on the SDRAM DIMM.
    > > The BIOS doesn't need to guess the correct timing values, it simply reads
    > > the EEPROM and programs the memory controller. In the case of a BIOS that
    > > doesn't use EEPROM you might lose data as the BIOS iteratively tries
    > > different memory timings and tests if they work.

    This would totally depend on your controller. But different timings
    shouldn't affect your memory cells just the read/write paths to your
    memory.

    > > I have done work implementing ACPI S3 (suspend-to-RAM) in DOS by simply
    > > hitting
    > > the RESET button and restoring the memory controller settings. The contents
    > > of
    > > RAM have always been valid.

    Hmm. That sounds a little risky. I have measured single bit errors
    occuring as early as 1s after writing the data without somekind of
    refresh running.

    > > David Christensen
    > >
    >
    > I just posted working SDRAM controller initialization code. The SDRAM
    > controller must be initialized in a specific step-by-step manner or
    > else you don't even get to "restoring the memory controller settings".

    Comments frequently don't match the code. And how the SDRAM controller
    must be initialized totally depends on the chipset and vendor. SDRAM
    itself must be initialized in a specific matter.

    But for the case of a warm reset there is not need to reset the SDRAM
    controller. Memory really only needs to be cleared in the case when
    some form of error checking is being used.

    Personally I think writing such code carries more credibility then
    simply posting it anyway....

    Eric
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