Messages in this thread | | | Date | Wed, 20 Jun 2001 18:53:05 -0400 | From | Charles Cazabon <> | Subject | Re: Threads FAQ entry incomplete |
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J.D. Bakker <bakker@thorgal.et.tudelft.nl> wrote: > At 13:42 -0600 20-06-2001, Charles Cazabon wrote: > >Rodrigo Ventura <yoda@isr.ist.utl.pt> wrote: > > > BTW, I have a question: Can the availability of dual-CPU boards for > > > intel and amd processors, rather then tri- or quadra-CPU boards, be > > > explained with the fact that the performance degrades significantly for > > > three or more CPUs? Or is there a technological and/or comercial reason > > > behind? > > > >Commercial reasons. Cost per motherboard/chipset goes way up as the number > >of CPUs supported goes up. For each CPU that a chipset supports, it has to > >add a lot of pins/lands, and chipsets are already typically land-limited. > > That's not quite accurate. Most modern SMP-able processors have a common > bus, where going from 1->2 CPUs adds just a handful of extra nets (usually > bus request, bus grant and some IRQs). The actual issues are threefold.
Low-end Intel multi-CPU chipsets are like this (typical 2-CPU configurations, and low-end 4-CPU configurations). Higher-end systems (8-way, etc) typically have multiple processor busses, with only one, two, or four processors per bus. Processor bus contention costs performance even in 2-way systems, and at 4-way and above, it becomes a serious bottleneck. High end chipsets do the cache coherency and snooping control between the busses. Other N-way chipsets (i.e., non-Intel) have point-to-point links between each CPU and the chipset. The new AMD 760 chipset for Athlon is like this; so are N-way Alpha chipsets. I can't swear to other hardware.
> First, most commodity chipsets simply support no more than two CPUs at best; > most CPUs don't support having more (or any) siblings. Adding more is cheap > on the ASIC level, but nobody bothers because there is no demand.
Ask ServerWorks about this. They make 16-way Intel chipsets. It's possible, just not cheap.
> Third, the more CPUs a bus holds, the higher the capacitance on the bus > lines. Higher capacitance means lower maximum bus speed, which aggravates > point two.
Which is one of the reasons for a pont-to-point "bus" with Alpha and Athlon CPUs.
Charles -- ----------------------------------------------------------------------- Charles Cazabon <linux-kernel@discworld.dyndns.org> GPL'ed software available at: http://www.qcc.sk.ca/~charlesc/software/ My opinions are just that -- my opinions. ----------------------------------------------------------------------- - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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