lkml.org 
[lkml]   [2001]   [May]   [4]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: Possible PCI subsystem bug in 2.4

On 4 May 2001, Eric W. Biederman wrote:
>
> There are a couple of options here.
> 1) read the MTRRs unless the BIOS is braindead it will set up that area as
> write-back. At any rate we shouldn't ever try to allocate a pci region
> that is write-back cached.

This one I'd really hesitate to use. We do _not_ want to trust the BIOS
any more than necessary (obviously trusting even the e820 was too much),
and especially wrt MTRR's we know that there are too many buggy bioses
already out there.

> 2) read the memory locations from the northbridge. It's not possible
> on every chipset (lack of documentation) but with the linuxBIOS
> project we code for a couple of them, and we are working on more
> all of the time.

This will be easy.

In fact, we can easily "mix" different heuristics. Ie we'd do the simple
thing I suggested in setup_arch(), and use that as a "base guess", and
then we can have incremental improvements on that guess that might be
chipset-specific or might depend on other information that is not
necessarily generic (things like existing PCI programming etc).

Linus

-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/

\
 
 \ /
  Last update: 2005-03-22 12:52    [W:0.157 / U:0.332 seconds]
©2003-2011 Jasper Spaans. Advertise on this site