Messages in this thread | | | Date | Fri, 9 Feb 2001 21:59:24 +0100 (MET) | From | "Maciej W. Rozycki" <> | Subject | Re: [PATCH] Re: UP APIC reenabling vs. cpu type detection o |
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On Fri, 9 Feb 2001, Petr Vandrovec wrote:
> > Why do you need to mask NMI at all? > > Because of you must provide some function which handles NMI, and as > you cannot switch IDT and CR3 atomically together, NMI handler has > to be on same address in both address spaces - at least temporary.
Can't it be?
> And in addition NMI handler in VM would have to switch address spaces > back, execute NMI handler, and return CPU/MMU back to previous state - > which may be just in the middle of normal VM<->Linux transition, so > this context switching cannot use any global variable, it must > save complete CPU/MMU state on stack. And it must not use any spinlock.
Do you need to pass NMIs to VM at all? NMIs as defined by the PC/AT architecture are delivered as a result of memory parity errors or ISA IOCHK errors. Is that functionality really needed in VM?
> If you have any idea how it can be done with NMI unmasked all the way > around...
It depends on the application -- you may avoid problems by careful coding and a nested NMI will never happen -- the CPU masks the NMI line internally, from accepting an NMI till a subsequent iret.
-- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available +
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