Messages in this thread | | | From | "Martin Eriksson" <> | Subject | [PATCH][highly-experimental] via-mwq (Was: Re: VIA acknowledges North Bridge bug...) | Date | Fri, 7 Dec 2001 11:28:47 +0100 |
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----- Original Message ----- From: "Calin A. Culianu" <calin@ajvar.org> To: "Petri Kaukasoina" <kaukasoi@elektroni.ee.tut.fi> Cc: <linux-kernel@vger.kernel.org> Sent: Thursday, December 06, 2001 11:09 PM Subject: Re: VIA acknowledges North Bridge bug (AKA Linux Kernel with Athlon
> Here is the webpage: > > This patch detects the 0305, 3099, 3102, and 3112 (KT133x, KT266x, VT8662, > and KLE133) *only*. On these chipsets, it will patch register 55 in the > Northbridge, which will supposedly switch off a Memory Write Queue timer. > In the KT133A datasheet, register 55 is "reserved". But - yikes! - in the > KT266, the documented MWQ register is register 95, not 55. Register 55 > contains unrelated DDR timing adjustments and could actually be dangerous > to program. For this reason, I do not recommend installing this driver on > the KT266x chipsets until VIA examines this issue. For now, use WPCREDIT > and set bits 5, 6, and 7 to zero in register 95 instead." > > ---- > > Clearly, we need to modify the via workaround patches to take into account > the other via device id's (namely 3099, 3102, and 3112), and for each one > change the appropriate register. Either register 55 or in the case of the > kt266x, register 95. I am grepping through quirks.c right now and it > seems this would be the correct file to modify.. any other suggestions on > what file to modify?
I've (hastily) put these changes into "arch/i386/kernel/pci-pc.c" and had to modify "include/linux/pci_ids.h" too.
The patch is included, but a warning: I have no VIA based computer that I can test this on myself...
_____________________________________________________ | Martin Eriksson <nitrax@giron.wox.org> | MSc CSE student, department of Computing Science | Umeå University, Sweden
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