Messages in this thread | | | Date | Mon, 5 Nov 2001 20:04:33 +0100 (CET) | From | Gérard Roudier <> | Subject | Re: 2.4.14-pre6 |
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On Mon, 5 Nov 2001, Josh Fryman wrote:
> > Basically, you get two virtual CPU's per die, and each CPU can run two > > threads at the same time. It slows some stuff down, because it makes for > > much more cache pressure, but Intel claims up to 30% improvement on some > > loads that scale well. > > > > The 30% is probably a marketing number (ie it might be more like 10% on > > more normal loads), but you have to give them points for interesting > > technology <) > > Specifically, the 30% comes in two places. Using Intel proprietary > benchmarks (unreleased, according to the footnotes) they find that a > typical IA32 instruction mix uses some 35% of system resources in an > advanced device like the P4 with NetBurst. the rest is idle. > > by using the SMT model with two virtual systems - each with complete > register sets and independent APICs, sharing only the backend exec > units - they claim you get a 30% improvement in wall-clock time. This > is supposed to be on their benchmarks *without* recompiling anything. To > get "additional" improvement, using code to take advantage of the dual > virtual CPUs nature of the chip and recompiling should give some > unquantified gain.
All things being equal, this probably will make a NxMHz P4 be as fast as a NxMHz PIII. But the new complexity it may require in real life may just turn the gain into just nil.
What a great improvement, indeed! :-)
Gérard.
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