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SubjectRe: Page Attribute Table (PAT) support?
Timur Tabi wrote:

> ** Reply to message from Jeff Hartmann <jhartmann@valinux.com> on Wed, 24 Jan
> 2001 11:45:43 -0700
>
>
>
>> I'm actually writing support for the PAT as we speak. I already have
>> working code for PAT setup. Just having a parameter for ioremap is not
>> enough, unfortunately. According to the Intel Architecture Software
>> Developer's Manual we have to remove all mappings of the page that are
>> cached.
>
>
> For our specific purposes, that's not important. We already flush the cache
> before we create uncached regions (via ioremap_nocache). I understand that as a
> general Linux feature, you can't ignore cache incoherency, but I don't think
> it's a hard requirement.

Actually you can't ignore it or the processor will have a heart attack
if the cached page mapping is used even speculatively. I've done some
experimenting, if the page is mapped cached in one place, and UCWC in
another, things will not work. Its extremely likely the processor will
cease to function. Its not like having cached and uncached mappings of
a page (which does work on the Intel processors, we use that feature in
the agpgart and the DRM in fact.) When you mark a page UCWC, you better
have removed all cached mappings or your asking for REAL trouble.

-Jeff

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