Messages in this thread | | | Date | Thu, 11 Jan 2001 12:41:12 +0100 (CET) | From | Ingo Molnar <> | Subject | Re: Oops in 2.4.0-ac5 |
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On Thu, 11 Jan 2001, David Woodhouse wrote:
> The bug here seems to be that we're using the same bit > (X86_FEATURE_APIC) to report two _different_ features.
i think that the AMD APIC is truly 'compatible', but we are trying to enable the APIC and program performance counters in an Intel-way. The MSRs can be incompatible between steppings of the same CPU, so we should not mark something 'incompatible' on that basis.
so the correct statement is: the UP-P6-specific way of enabling APICs does not work on Athlons. It doesnt work on P5's either.
Ingo
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