[lkml]   [2000]   [Aug]   [28]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
    SubjectRe: [patch] waitqueue optimization, 2.4.0-test7
       Date: 	Mon, 28 Aug 2000 19:09:00 +0200 (CEST)
    From: Andrea Arcangeli <>

    On IA32 at least UnlockPage can't trigger the race because there's
    the lock on the bus to do the clear_bit, but for example on the
    alpha we do the clear bit with the load locked store conditional
    operations (same thing on sparc64), thus we don't put any memory
    barrier anymore between clearing the bit and reading the waitqueue.

    This is not correct on sparc64, no younger loads can bypass the atomic
    compare&swap operation. I bet the same is true for
    load_locked+store_conditional on Alpha and MIPS. Did you check what
    semantics Alpha guarentees in the reference manual (or more
    importantly what the Alpha cpus really do)? I know you have a copy of
    it and do read it Andrea ;-)))

    I really cannot imagine a chip allowing the waitqueue_empty read to
    occur before the ll/sc sequence, that would make no sense at all and
    be very difficult silicon to even implement.

    David S. Miller
    To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
    the body of a message to
    Please read the FAQ at

     \ /
      Last update: 2005-03-22 12:38    [W:0.019 / U:204.104 seconds]
    ©2003-2017 Jasper Spaans. hosted at Digital OceanAdvertise on this site