Messages in this thread | | | From | (Linus Torvalds) | Subject | Re: Cache coherency... and locking | Date | 30 Jul 2000 22:37:21 -0700 |
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In article <Pine.LNX.4.10.10007272155260.20583-100000@waste.org>, Oliver Xymoron <oxymoron@waste.org> wrote: >On Thu, 27 Jul 2000, Linda Walsh wrote: > >> Some followup -- it was setting/testing 1 integer. So it >> seems it can safely be done w/o lock. > >Cool. > >> Talking with an internal engineer here -- NUMA uses MESI >> cache control similarly to the i386 cache coherency model, >> so a write of one CPU to a an area of memory will be seen >> on other processors as soon as they ask for that memory. > >That's specific to MIPS. A general Linux NUMA model probably won't assume >coherence.
I disagree.
If it's not ccNUMA, then the different nodes should run _different_ copies of the OS, and you'd basically have a multi-OS system rather than single image. Non-cache-coherent hardware simply is not worth handling as a single image, I suspect.
So at least right now my personal plan would be to consider non-cc NUMA to be just a cluster. Multiple machines backed with a fast interconnect, and communication between them happens as if they were separate machines (and the fast interconnect is then used as a way to make those separate machines able to communicate with each other really well).
Most current/modern NUMA designs are ccNUMA anyway, as far as I can tell. I don't know of anybody who seriously makes a non-cc machine any more. People know how to make efficient cache controllers, and it just makes the machines _soo_ much more usable that anybody who isn't cache coherent really deserves to be ridiculed.
Linus
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