Messages in this thread |  | | | Date | Mon, 31 Jul 2000 15:20:41 -0500 (CDT) | | From | Oliver Xymoron <> | | Subject | Re: Cache coherency... and locking |
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On 30 Jul 2000, Linus Torvalds wrote:
> In article <Pine.LNX.4.10.10007280922170.20318-100000@waste.org>, > Oliver Xymoron <oxymoron@waste.org> wrote: > > > >Because cache coherence is both complex and expensive and treating a NUMA > >as a tight cluster rather than a single machine (as you mention) is > >probably a saner architecture. > > This is not necessarily all that true any more. People have gotten > better at doing cache coherency, and there are people who want to try > it. Let them. > > Yes, I suspect that for true scalability you _do_ want to consider the > machine to be a tight cluster. However, I don't think it's unreasonable > to do a ccNUMA architecture of, say, 4x4 (four nodes with 4 CPU's each), > and use it in an SMP manner.
Agreed. I should read all my mail before replying..
> Such a setup doesn't actually _have_ to be expensive - assuming standard > chipsets were to come out etc. Remember what made SMP cheap.
NT support? Heh. The most likely route for cheap PC NUMA is 200+ Mhz memory buses (Athlon and P4 systems), 64-bit PCI-66 and the like (server disk subsystems will probably make this a desktop reality), and bus bridges made to replace gig ethernet in Beowulfs..
-- "Love the dolphins," she advised him. "Write by W.A.S.T.E.."
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