Messages in this thread | | | Subject | Re: [PATCH] i386 tlb flush bug fix | From | David Wragg <> | Date | 20 Jul 2000 11:31:36 +0000 |
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Manfred <manfred@colorfullife.com> writes: > I found a tlb flush race in switch_mm: > > If > * the cpu is in lazy tlb mode > * it perform a thread switch without changing active_mm. > * a flush ipi arrives while the cpu is in switch_mm, after the > set_bit(cpu_vm_mask), but before setting cpu_tlbstate[].state. > > then the cpu will miss all tlb flush ipis until the next reschedule.
Yes, this is it. This morning I tried changing the tlbstate accesses in switch_mm() to use xchg(), to make them atomic w.r.t. the flush ipi, and it fixed the problem.
But getting rid of the OLD state completely seems like a neater solution.
> > My first bugfix left a tiny race, below is a new bugfix. > > I've tested it on my Dual-pII, but I don't have any special multi threaded > test apps. > > Please test it!
I'll try it this evening and let you know how it goes. Thanks for looking at the problem.
David Wragg
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