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    SubjectRe: i8259 IRQ problems
    On Fri, 24 Mar 2000, Manfred Spraul wrote:

    > > CPUs can implement priority ordering in the local apic but
    > > currently don't.
    > Are you sure?
    > The Intel PPro documentation isn't very clear - but docu is never clear
    > about deficiencies of the product :-/

    There is no way to disable priorities in the APIC, sigh. Higher priority
    interrupts get dispensed first. If an interrupt is in service, lower
    priority interrupts are not dispensed at all until the service finishes.
    By "dispensing" I mean asserting the APIC's PINT output, which in turn is
    tied to the CPU's INT input (internally for the integrated APIC). This is
    consistent with Intel's docs.

    > > A local APIC won't accept another interrupt while the CPU has interrupts
    > > disabled.
    > Are you sure?
    > The "Interrupt Acceptance Flow Chart for the Local APIC" doesn't contain
    > the "Interrupt Enabled" flag of the associated cpu.

    The local APIC have no idea of the status of the IF flag in the CPU. How
    would it know? It's only communicates via INT, NMI, INIT and SMI with the
    CPU (though I think there is a backdoor for StartUp IPIs as well).

    I agree the documentation for the integrated APIC is rather sparse. Docs
    for the 82489DX APIC are much better (but note that the chips differ
    significantly in some areas) -- the datasheet is 82 pages thick and is
    rather extensive and there is also a 22-page programming manual -- but
    they are hard to obtain these days.

    --
    + Maciej W. Rozycki, Technical University of Gdansk, Poland +
    +--------------------------------------------------------------+
    + e-mail: macro@ds2.pg.gda.pl, PGP key available +


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