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SubjectRe: [patch-2.3.46-p2] P6 microcode update support
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Tigran Aivazian <tigran@aivazian.fsnet.co.uk> said:

[...]

> Also, more importantly, Intel manual says "the update must run in the
> early stages of POST and always before L2 cache controllers are
> initialized". I ignored it and it still worked fine. However, on the bus
> to work this morning I thought "perhaps I should use some MSRs to
> disable cache and re-enable it?". I will think on this in the background
> but first rewrite it as a char driver.

Why not a standalone program to do this? I assume the microcode gets loaded
into non-volatile memory in the CPU, so this would be definitely be better
as an off-line operation. The kernel hasn't got hooks for upgrading BIOS
either...

Or place it into the boot process, i.e., lilo(8), or the early stages of
bootstrap of the kernel itself. This would make sense given the above
restriction (which might not be in force with _your_ CPU, but for others).

If none of the above this an option, I'd vote for a non-ia32 specific name,
so other CPUs with this option can reuse it. /dev/mcde? /dev/mud? /dev/cpumu?
--
Horst von Brand vonbrand@sleipnir.valparaiso.cl
Casilla 9G, Viña del Mar, Chile +56 32 672616

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