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SubjectRe: Port of 3c575_cb to 2.3.43pre8
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> If a hardware device asserts its interrupt line long enough for the
> interrupt controller to see it, it is latched. That is how the interrupt
> controller 'remembers' that an interrupt occurred. It doesn't care
> if the interrupt line is deasserted before the CPU is notified. In fact,
> because of the priority of higher-priority pending interrupts the
> CPU probably won't know about it right away. That's why any pending
> hardware interrupts are latched.
>
> I do know about this chipset.

Well the man at Intel who documented it, the guys at IBM who designed the PC
and the folks at Novell whose drivers include hooks for it, and a friend who
designs boards all disagree with you.

Somehow I trust them. Especially as I've seen it happening.

Alan


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