[lkml]   [2000]   [Nov]   [2]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
    SubjectRe: Dual XEON - >>SLOW<< on SMP
    On 2 Nov 2000, Ulrich Drepper wrote:

    > I'm seeing this as well, but only with PIII Xeon systems, not PII
    > Xeon. Every single timer interrupt on any CPU is accompanied by a NMI
    > and LOC increment on every CPU.
    > CPU0 CPU1
    > 0: 146727 153389 IO-APIC-edge timer

    This is the legacy 8254 timer source, used for the system time, i.e.
    gettimeofday() and friends.

    > NMI: 300035 300035

    This is the NMI watchdog at work. Every tick of the legacy timer all
    CPUs receive an NMI unless overridden by the "nmi_watchdog" command line

    > LOC: 300028 300028

    This is the internal local APIC timer used for scheduling. Every CPU is
    equipped with such a private timer.

    + Maciej W. Rozycki, Technical University of Gdansk, Poland +
    + e-mail:, PGP key available +

    To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
    the body of a message to
    Please read the FAQ at

     \ /
      Last update: 2005-03-22 12:45    [W:0.021 / U:9.380 seconds]
    ©2003-2017 Jasper Spaans. hosted at Digital OceanAdvertise on this site