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SubjectRe: Dual XEON - >>SLOW<< on SMP
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"Richard B. Johnson" <root@chaos.analogic.com> writes:

> Yes. Look at the NMI count. Looks like every access produces a
> NMI.

I'm seeing this as well, but only with PIII Xeon systems, not PII
Xeon. Every single timer interrupt on any CPU is accompanied by a NMI
and LOC increment on every CPU.

CPU0 CPU1
0: 146727 153389 IO-APIC-edge timer
[...]
NMI: 300035 300035
LOC: 300028 300028


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