Messages in this thread | | | Subject | Re: Linux and real device drivers | From | Jes Sorensen <> | Date | 22 Sep 1999 10:54:19 +0200 |
| |
>>>>> "Momchil" == Momchil 'Velco' Velikov <velco@fadata.bg> writes:
Momchil> Jes Sorensen wrote: >> pre-fetching, write-back caching, nobody said all PCI writes have >> to be synchronous. No I don't really care about I/O port access.
Momchil> Are you kidding? Do you really want to use that on device's Momchil> registers ?
Oh yes, very much indeed. If you are writing data to a buffer descriptor in PCI shared memory space, there is no reason to do every single write synchronously when all you want is to make sure that all data is there before you issue the `send' command to the adapter.
>> Faster your processor, the deeper your pipeline, branch == >> pipeline flush. next?
Momchil> Ok, branch has a penalty but it's certainly != pipeline Momchil> flush. Note that this is unconditional branch, and if the Momchil> branch target address is computed sufficiently ahead of the Momchil> branch instruction there will be no penalty.
Depends on your architecture.
>> And here you might want to look at some of the released >> documentation on the IA64 to see what we might expect from the >> future, branches are expensive.
Momchil> Have Intel released docs about some implementation of the Momchil> architecture ? OTOH, judging from past experience, I wan't Momchil> be surprised if Intel ain't got it Right *again*. (OK, OK, Momchil> just kidding, people (and companies) sometimes grow up and Momchil> learn things :-)
Well take a look at it, it's actually quite neat - http://developer.intel.com/design/ia64/downloads/adag.htm
Jes
- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.rutgers.edu Please read the FAQ at http://www.tux.org/lkml/
| |