Messages in this thread | | | Date | Wed, 25 Aug 1999 02:58:36 +0200 | From | Ralf Baechle <> | Subject | Re: Cache incoherencies (WAS: New resources - pls, explain :-( ) |
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> > In order to make something compilable on both coherent and incoherent > > archs, we should standardize the #define for the cache line size, add a > > routine/macro to query about the coherency of the bus, and provide a > > "magic" bit for kmalloc that gives you non cachable space.
A per bus coherency isn't sufficient. There are architectures which can set cache coherency on a per device base. On SMPs this can avoid a major amount of cross-CPU invalidates, therefore a good performance gain. For architectures like this you want to leave the decission to the driver writer.
Ralf
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