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    SubjectAnother Athlon MTRR patch
    Hi!

    In my previous Athlon patch (mail subject: Two MTRR patches)
    I overlooked one thing: there is an Intel PPro revision
    check in mtrr_add() which is (of course) only valid for Intel.

    By putting the AMD branch before Intel, the code checked the
    Athlon revision as well. This patch fixes it by double checking
    the vendor.

    Zoltan Boszormenyi--- mtrr.c-Athlon Sat Aug 14 09:31:44 1999
    +++ mtrr.c Sun Aug 15 20:41:12 1999
    @@ -218,6 +218,9 @@
    Rearrange switch() statements so the driver accomodates to
    the fact that the AMD Athlon handles its MTRRs the same way
    as Intel does.
    + 19990814 Zoltan Boszormenyi <zboszor@mol.hu>
    + Double check for Intel in mtrr_add()'s big switch() because
    + that revision check is only valid for Intel CPUs.
    */
    #include <linux/types.h>
    #include <linux/errno.h>
    @@ -1104,12 +1107,15 @@
    break;
    } /* else fall through */
    case X86_VENDOR_INTEL:
    - /* For Intel PPro stepping <= 7, must be 4 MiB aligned */
    - if ( (boot_cpu_data.x86 == 6) && (boot_cpu_data.x86_model == 1) &&
    - (boot_cpu_data.x86_mask <= 7) && ( base & ( (1 << 22) - 1 ) ) )
    - {
    - printk ("mtrr: base(0x%lx) is not 4 MiB aligned\n", base);
    - return -EINVAL;
    + /* Double check for Intel, we may run on Athlon. */
    + if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
    + /* For Intel PPro stepping <= 7, must be 4 MiB aligned */
    + if ( (boot_cpu_data.x86 == 6) && (boot_cpu_data.x86_model == 1) &&
    + (boot_cpu_data.x86_mask <= 7) && ( base & ( (1 << 22) - 1 ) ) )
    + {
    + printk ("mtrr: base(0x%lx) is not 4 MiB aligned\n", base);
    + return -EINVAL;
    + }
    }
    /* Fall through */
    case X86_VENDOR_CYRIX:
    \
     
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