Messages in this thread | | | Date | Sat, 31 Jul 1999 20:27:04 +0200 (NST) | From | jelle@flying ... | Subject | Re: [PATCH] HZ=100 assumptions |
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On Fri, 30 Jul 1999, Riley Williams wrote:
> Hi there.
Hi!
> > Just some observations. > > > 65536 ticks per hour would be approx 18.2hz, which definitely > > can't be true. > > It's not hard to check that out and find that it IS true.
14.31818Mhz/12/65536=18.2065Hz. Damn I made a miscalculation, you are obviously correct. I stand corrected for that remark.
The 14.31818Mhz, the approx. 18.2Hz, the original PC/XT's 4.77Mhz, and NTSC colours, they are all connected.
> For many > years, the biggest complaint about the IBM PC and its clones was that > the system heartbeat was so slow, and people had to play tricks to get > a decent interval timer. That's also not hard to prove.
... And the document I refer to below explains what tricks you can do in detail with example source code, images and all.
However, I don't see what that has to do with that the timer tick is *not* a result from a choice of 65536 ticks per hour, but a result of four times the NTSC colour sub carrier divided by 12*65536 (which results in approx 65543 ticks per hour btw).
Find "FAQ / Application notes: Timing on the PC family under DOS", in the file msdos/info/pctim003.zip on simtel, and it will tell you about the hardware and which confirms what I said in my last mail, including the independent clock source for the CMOS clock. The pctim003.zip archive also contains some nice explanatory images about the original PC hardware structure.
--- excerpt from pctim003.txt ----
## 2.1 THE BIG PICTURE
The 14.31818 MHz system clock is divided by 12 to give a 1.193182 MHz clock (period is 0.8381 microseconds) which clocks the three channels of the 8253/8254 counter/timer chip (CTC). The CTC divides this frequency to lower frequencies using programmable divisors, and produces three output signals.
CTC channel zero's output is connected directly to IRQ0 on the primary PIC (8259 interrupt controller chip), and generates int 8, the timer tick interrupt, about 18.2065 times per second, or once every 54.9254 milliseconds. The timer tick is a regular interrupt which allows certain actions (such as updating the system time-of-day) to be executed periodically.
Interrupt 8 is serviced by the ROM-BIOS. The BIOS's int 8 handler increments the BIOS tick count variable (a 32-bit variable used for timekeeping) and turns off the floppy disk drive motors two seconds after they were last accessed. It also issues int 1C hex, which may be used as a regular interrupt source by user programs.
The BIOS tick count is a 32-bit counter at low memory address 0040:006C, which contains the number of timer ticks (units of 54.9254 ms) since midnight and is used by DOS to calculate the time of day.
CTC channels 1 and 2 can also be used for timing, via the Refresh Detect and Timer 2 readback signals on Port B. Channel 2 also generates audio for the PC speaker, and can be used in conjunction with channel 0 for PWM audio generation.
The CTC divides its 1.193182 MHz clock down to 18.2065 Hz using a 16-bit counter. It is possible to read the actual count in progress in the CTC. In combination with the tick count variable, this can give an absolute time value, in units of 0.8381 us, for timestamping, elapsed time calculation, etc.
In some applications, a timer tick rate faster than 18.2065 times per second is required. This can be achieved by reprogramming the CTC. The CTC is told to generate the timer tick at a faster rate, and the program intercepts the timer tick interrupt (int 8). The int 8 handler does its thing, and calls the old int 8 handler at the correct rate (18.2065 times per second) to maintain the correct system time.
The Real Time Clock (RTC) was introduced with the AT, and all hardware- compatible ATs and later machines have one. The RTC is completely independent of the CTC. It uses a 32.768 kHz watch crystal for timekeeping and is battery backed up (i.e. continues to keep time while the computer is powered off). It can be used to generate a periodic interrupt, usually at 1024 Hz (1024 interrupts per second).
--- SNIP ---
## 7.1 THE 14.31818 MHZ CLOCK
A crystal oscillator or oscillator module generates a 14.31818 MHz clock which is divided by 12 to give the 1.1931816666666... MHz clock frequency (period is 12/14318180, or 0.83809534452 us), which is fed to all three channels of the counter/timer chip. This is the basic timing resolution of the counter/timer.
## 7.2 CLOCK FREQUENCY ACCURACY
The 14.31818 MHz clock's absolute accuracy depends mainly on the quality of the 14.31818 MHz crystal or crystal oscillator module, and is typically in the region of +/- 5 ppm (0.0005%; 0.4 seconds per day) to +/- 20 ppm (0.002%; 1.73 seconds per day). Errors consist of initial frequency error, and variations due to temperature and long-term drift. Because of these inaccuracies, there is little point in specifying times or frequencies to more than five or six digits as I have done above.
If required, frequency accuracy can be improved by installing a high quality, close-tolerance crystal, or a high quality crystal oscillator module, which will reduce all of the above error sources. If accuracy is still inadequate, with a crystal it may be possible to add a small variable capacitor to the oscillator circuit, to 'pull' the crystal onto the correct frequency. If anyone has specific advice on this, please let me know. (*)
Alternatively, your software could incorporate an adjustment so that once the amount of error has been measured, manually by the user over a long period of time, it could be corrected by the software. Of course this must be configured individually for every machine the software will run on, and temperature and long term drift will still have an effect.
Historical note: If you were wondering "Wouldn't 1 MHz have been easier?", yes it would, but that would have required an extra crystal. IBM were... er, 'clever' - they used a master clock of 14.31818 MHz, and used logic chips to derive the 4.77 MHz CPU clock, the timer clock, and the NTSC colour subcarrier frequency for the CGA card, so they could save a few dollars. Although the 14.31818 MHz signal is not required by modern CPUs and video cards (in fact, it is now only used for the CTC clock!), the strange frequency still hangs around like a stale fart - we are stuck with it forever. :-(
--- SNIP ---
## 7.4 CTC CHANNELS
Each channel operates independently, and can be programmed for one of six modes of operation. Normally, modes 2 or 3 are used. In these modes, the CTC channel takes the CTC clock (1.193182 MHz) and 'divides' this frequency down to produce a lower frequency at the output pin. Other modes operate differently.
The frequency division is controlled by the 'divisor' value, a 16-bit unsigned number between 1 and 65536 (65536 is represented as zero), which is individually programmable for each channel in the CTC. Setting a very small divisor value gives a very high output frequency. A divisor of 65536 gives the lowest output frequency, 18.206507364909 Hz (cycle period is 54.92541649846559 ms).
## 7.4.1 CTC CHANNEL ZERO
CTC channel zero normally operates in mode two or three with a divisor of 65536, giving an output frequency of 18.2065 Hz (period is 54.9254 ms). Its gate input is tied high. Its output drives the IRQ0 input of the primary PIC (8259 interrupt controller chip). On every rising edge of the channel zero output pin (i.e. transition from low to high), IRQ0 is triggered, invoking interrupt 8, the timer tick interrupt (see section <AF><AF> 6.1).
--- end excerpt from pctim003.txt ---
> Incidentally, the reason for that 65536 ticks per hour was because of > the way IBM's programmers designed the system timer - one word to > count the number of ticks, and a second to count the number of hours > that had passed...
That is wrong. There are close to 65543 ticks per hour (60*60*14.31818e6/65536/12).
How else would you explain that a 14.31818Mhz crystal can be found in a system with a 8253/8254 clock chip in its hardware that has no divider higher than 65536?
Let's look at pin 30B is the standadizes PC104 (~=ISA) connector http://users.desupernet.com/sokos/ISA.TXT, other reference http://nctnico.op.het.net/docs/isabus.txt)
B30 OSC High-speed clock (70 ns, 14.31818Mhz),50%duty cycle Out
OSC: Oscillator, 14.318 MHz, 50% Duty Cycle. Frequency varies. This was originally divided by 3 to provide the 4.77 MHz cpu clock of early PCs, and divided by 12 to produce the 1.19 MHz system clock. Some references have placed this signal as low as 1 MHz (possibly referencing the system clock), but most modern systems use 14.318 MHz. This frequency (14.318 MHz) is four times the television colorburst frequency. Refresh timing on many PC's is based on OSC/18, or approximately one refresh cycle every 15 microseconds. Many modern motherboards allow this rate to be changed, which frees up some bus cycles for use by software, but also can cause memory errors if the system RAM cannot handle the slower refresh rates.
> Best wishes from Riley. > > +----------------------------------------------------------------------+ > | There is something frustrating about the quality and speed of Linux | > | development, ie., the quality is too high and the speed is too high, | > | in other words, I can implement this XXXX feature, but I bet someone | > | else has already done so and is just about to release their patch. | > +----------------------------------------------------------------------+ > * ftp://ftp.MemAlpha.cx/pub/rhw/Linux > * http://www.MemAlpha.cx/kernel.versions.html > >
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