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SubjectRe: EPIC
On Sun, Jun 06, 1999 at 04:02:27PM +0200, Erik Corry wrote:
> "Matti Aarnio" <19990606155651.R30475@mea.tmt.tele.fi> wrote:
> > per single clock cycle. EPIC in itself does not give you
> > anything special, likely it will cause more constraints to
>
> Did you read the PDF file on Merced before saying this?

No, when such has appeared ? ... A week ago ?

Now that I have browsed a bit of that document which you
referred here, I still don't think it supplies anything
special. In fact I think it is in amazingly lots of ways
like SPARCs are.

128 integer registers, 128 FP registers, and lots of
other user-level registers, many of which need saving
in context switches ... Looks like intel has joined
SPARC family in register window technology (there was
a note about register windowing exploitable at function
calls), and various pains which relate to massive amounts
of registers to be saved/loaded during a context switch.

Where ia-32 is register-poor, at least its context switches
are fairly fast...

The instruction format expects 3+1 longwords (32-bits each)
worth of instruction stream data, and although its ways
to explicitely combine integer and float instructions are
more versatile (=complicated) than what DEC 21264 Alpha
can do, it can barely match said Alpha processor in speed
of instructions per clock cycle. (That alpha can do up
to 2i+2fp instructions per clock.)

Sure it can do wonders for a speed-daemon usages, like me
using pico to edit email, but a 386 can do that too...

Getting the best out of that instruction format in applications
does require lots of smarts in the compiler, and (I hazard a
guess) application which does lots of things without frequent
function calls, or system calls.

There definitely is no amazing magic bullet to speed things
up tremendously. It might be a decent tool for heavy computing
environments, but it is not alone at it.

> --
> Erik Corry erik@arbat.com Ceterum censeo, Microsoftem esse delendam!

/Matti Aarnio <matti.aarnio@sonera.fi>

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