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    SubjectRe: [2.2.8] undefined reference to `disable_irq_nosync' (+ fix)

    On Fri, 14 May 1999, Matthew Wilcox wrote:

    > I had a cunning thought a couple of weeks back which people seem to think
    > will work, but no-one's done yet :-)
    > The problem is that if the SWP instruction (atomically read-and-write)
    > hits in the cache, it will not go through to main memory, unlike earlier
    > ARM processors. Obviously, disabling the cache is going to take a big
    > performance hit (particularly for those of us with 33MHz busses, argh).

    Grrrmmm... Somewhere I've heard about SMP on a beast with really sucking
    cache coherency... Wait a bit... Yup. Processor in question: KL-10.
    OS: TOPS-10. They had a nasty time fighting with that problem and there
    is a good paper on about the
    thing they did.

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