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    SubjectRE: spin_unlock optimization(i386)
    > Nope.
    > Because when CPU0 reads 1 from valid, the value read is still
    > not retired (i.e. committed) and at this point it sees that value is
    > set to 45 (because it couldn't have seen valid=1 before seeing value=45
    > since writes are not reordered). So it will re-exec the read of value
    > (because the not-yet-committed-read is still around and its address
    > is matched to the incoming writes, allowing to detect such problems).
    > Now I don't know if this is part of x86 or only P6 since
    > supposedly the P6 provides a slightly stronger consistency model.
    > Also this solves the present case but not the one I sent earlier
    > because no CPU needs to see any of the other's writes, so the
    > instructions can all be retired before any communication takes place.

    I couldn't find this guaranteed in the architecture manual, so I would
    assume that it's specific to certain models. It's worth taking advantage of
    these optimizations on chips where they're known to be safe.


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