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SubjectRe: spin_unlock optimization(i386)
On Wed, 24 Nov 1999, Erich Boleyn wrote:

>Make the variables "volatile" and the compiler is required by the ANSI

Yes of course. current->state is _just_ volaile. Making a variable
volatile or putting a barrier() between the load/stores make no
difference.

>ALL SMP-visible or memory-mapped hardware variables should in general be
>"volatile" to make sure you get exactly what you're asking for from the
>compiler.

That's just so in 2.2.x of course. The assembler we generate is written in
the wanted order by using volatile attributes or barrier()s.

>weaker case of Processor Ordering for Writeback (WB) memory (where stores
>can be arbitrarily delayed from the other processors). This means you

Actually we don't care at all about the delay of writes, as the delay can
be seen as the other processor running a bit slower for example. We don't
depend on the speed of the other CPUs or on the point of execution of the
other CPUs of course. In most cases the only thing we care is the order of
_reads_ and of _writes_. Nothing more. It seems by reading your email that
we are wasting time adding explicit memory barriers with lock on the bus
to enforce ordering on IA32. So I believe we can remove them as the
hardware is enforcing ordering for us.

Thank you. (I'll fix this soon...)

Andrea


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