Messages in this thread | | | Date | Thu, 28 Jan 1999 17:47:59 +0100 (CET) | From | MOLNAR Ingo <> | Subject | Re: Variability in cache access times |
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On Thu, 28 Jan 1999, David S. Miller wrote:
> I was wondering if that would be the response. What about using 4 MB > pages? Would that help? > > It would, but I have no idea how feasible this is with the Intel page > tables. Ingo could probably more quickly cook up a test patch than > me.
it's not particularly hard, especially since in the given case we have control over the application. i will write a small testpatch soon to create a '4MB mapped RAMDISK' at boot time, this can then be mmap()-ed directly. (i've had requests for this from other people as well) The 'generic' case is hard and up to debate wether it should be in the generic kernel. (my feeling is it shouldnt, it complicates things unnecessarily) And there is only limited application-side complexity. anyway, let the numbers talk first. I also have the feeling that a really smart page-coloring algorithm is superior to 4MB pages, as with 4K granularity we have _much_ more control over resolving cache conflicts automatically.
-- mingo
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