Messages in this thread | | | Date | Wed, 12 Aug 1998 10:59:19 -0700 | From | Richard Henderson <> | Subject | Re: interrupt latency |
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On Wed, Aug 12, 1998 at 09:30:31AM +1200, Chris Wedgwood wrote: > Actually... might just go and code something like that now. If > anybody knows the equivalent of `rdtsc' for the Alpha and Sparc I'd > really like to know that.
Alpha:
unsigned int x; asm volatile ("rpcc %0" : "=r"(x));
Yes, the (active) part of the counter is only 32-bit wide. Yes that does mean overflow in 8.1 seconds on a 500Mhz box. This traded for the ability to get virtual cycle counts:
unsigned long x; asm volatile ("rpcc %0" : "=r"(x)); x = (unsigned int)x + (unsigned int)(x >> 32);
I'm not sure it was worth it, personally.
UltraSparc:
unsigned long x; asm volatile ("rd %tick, %0" : "=r"(x));
Earlier Sparcs do not have this feature.
r~
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