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SubjectRe: 2.1.111: IDE DMA disabled...BLAH...BLAH...

Greetings All from the other Andre,

There is Andrew Derrick Balsa aka "Andre" and me "Andre".

As for the (U)DMA question, would it not be sensible for us to flag
the drive capablities. This below is part of a hack-job that I use to
try and tune the HPT343 UDMA chipset during boot.

static void config_drive_xfer_rate (ide_drive_t *drive)
{
const char **list;
byte xfer_mode = 0x00, xfer_dma = 0x00, xfer_pio = 0x00;
struct hd_driveid *id = drive->id;
#if IDEDMA_BASE_DEBUG_DMA
ide_hwif_t *hwif = HWIF(drive);
struct pci_dev *dev = hwif->pci_dev;

if ((dev->device == PCI_DEVICE_ID_TTI_HPT343) && (drive->using_dma)) {
(void) hwif->dmaproc(ide_dma_off, drive);
}
#endif /* IDEDMA_BASE_DEBUG_DMA */
if (id && (id->capability & 1) && !hwif->no_autodma) {
if (drive->using_dma) {
/* UltraDMA */
if ((id->field_valid & 4) &&
(id->dma_ultra & (id->dma_ultra >> 8) & 7)) {
xfer_mode = 0x04;
xfer_dma = (id->dma_ultra & 4) ? 0x02 :
(id->dma_ultra & 2) ? 0x01 : 0x00;
}
/* regular DMA multi-word */
if ((id->field_valid & 2) && (id->dma_mword & 0x404) == 0x404) {
xfer_mode = 0x02;
xfer_dma = (id->dma_mword & 4) ? 0x02 :
(id->dma_mword & 2) ? 0x01 : 0x00;
}
/* regular DMA single-word */
if ((id->field_valid & 2) && (id->dma_1word & 0x404) == 0x404) {
xfer_mode = 0x01;
xfer_dma = (id->dma_1word & 4) ? 0x02 :
(id->dma_1word & 2) ? 0x01 : 0x00;
}
/* Consult the list of known "good" drives */
list = good_dma_drives;
while (*list) {
if (!strcmp(*list++,id->model)) {
xfer_mode = 0x01;
xfer_dma = 0x01;
}
}
} else if ((id->capability & 8) || (id->field_valid & 2)) {
unsigned short eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
unsigned short timing = id->eide_pio_modes;
xfer_mode = 0x00;
if (timing > 4)
timing = 0;
if (id->eide_pio_iordy > 0) {
for (timing = 5;
timing>0 &&
id->eide_pio_iordy>eide_pio_timing[timing];
timing--);
} else {
timing = (id->eide_pio_modes & 4) ? 0x05 :
(id->eide_pio_modes & 2) ? 0x04 :
(id->eide_pio_modes & 1) ? 0x03 : timing;
}
xfer_pio = (byte) timing;
}
#if IDEDMA_BASE_DEBUG_DRIVE_INFO
printk("%s: %s %d\n", drive->name,
(xfer_mode & 4) ? "UDMA" :
(xfer_mode & 2) ? "DMA" :
(xfer_mode & 1) ? "DMA" : "PIO",
xfer_mode ? xfer_dma : xfer_pio);
#endif /* IDEDMA_BASE_DEBUG_DRIVE_INFO */
config_chipset_for_dma (drive, xfer_mode, xfer_dma, xfer_pio);
}
This is a modifcation of ML's original in "ide-dma.c",
"static int config_drive_for_dma (ide_drive_t *drive)"

This could be part of a model for tuning buggy bios chipset that
need PIO settings if (U)DMA is dissable, since the (id->media != ide_disk)
for many other things. One may need to force change the bios settings for
onboard PIIX's that see that a CDROM, ZIP, or TAPE is (U)DMA capable, but
is dissabled since they are not "disks". This is referring to
(hwif->dmabase+2) with masks 0x20 and 0x40.
Since some drives are (U)DMA capable at different levels, should the
kernel not be aware of this, and react based on a dynamic configuration
verses a generic DMA enable?

(U)DMA settings 0/1/2, that can be multi or single word, may have a need
for differnet timing requirements, is my main point.

One of the post tuning cases that I know of is for VIA chipsets, pointed
out by Michel Aubry which looks something like this ::

static int set_via_timings (pci_dev *dev, byte post, byte flush)
{
byte via_config = 0;
int rc = 0;
/* setting IDE read prefetch buffer and IDE post write buffer */
if ((rc = pci_read_config_byte(dev, 0x41, &via_config)))
return (1);
if ((rc = pci_write_config_byte(dev, 0x41, via_config | post)))
return (1);
/* setting Channel read and End-of-sector FIFO flush: */
if ((rc = pci_read_config_byte(dev, 0x46, &via_config)))
return (1);
if ((rc = pci_write_config_byte(dev, 0x46, via_config | flush)))
return (1);
return (0);
}
which should be called after "ide_setup_dma"

if (dma_base) {
ide_setup_dma(hwif, dma_base, 8);
if (IDE_PCI_DEVID_EQ(d->devid, DEVID_VP_IDE)) {
byte post = hwif->channel ? 0xc0 : 0x30;
byte flush = hwif->channel ? 0xa0 : 0x50;
set_via_timings(dev, post, flush);
}
}
BLAH...BLAH...

If someone will pass on some information about that buggy CMD640B card,
I will suffer a few crashes to help get the DMA up and running, but I need
jumper settings and all.

I have the following (U)DMA cards and chipsets to play/work with
AEC6210UF UDMA (modified SCSI)
PDC20246 UDMA
HPT343 UDMA (modified SCSI, non-booting)
CMD640B (no docs, drivers, or jumper settings)
PIIX3 and PIIX4
(Hopefully Soon)
FasTrax Raid UDMA
IDE Express UDMA (IEEE 1394)?

a pile of devices Quantum ST3.2 ST6.4 SE8.4, Maxtor AP2.0 A1.6,
WD 325's 4.3 6.4, Conner 420 1.6, Sony CDU611, NEC CD 2.61 4x4,
ZIP 23.D fw, Colorado 5G Tape, and some other junk.


Cheers,
Andre

Did I miss the discussion again??


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