Messages in this thread | | | Date | Fri, 10 Jul 1998 20:59:38 -0400 (EDT) | From | "Richard B. Johnson" <> | Subject | Re: Future time |
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On Sat, 11 Jul 1998, Maciej W. Rozycki wrote:
> On Fri, 10 Jul 1998, Richard B. Johnson wrote: > > > We need to use timer-channel 0, connected to IRQ0 for context-switches > > because it's the highest priority interrupt. However, we could use the > > CMOS timer, which is connected to a lower-priority interrupt, for the > > jiffy-counter and basic time functions. Or the PLL attempt, really > > a frequency-lock, already implemented, could sync to the CMOS timer. > > Hey, what's the problem with reprogramming the 8259s so that IRQ8 were > the highest priority interrupt? > > -- Well, for one, its connected to the first chip through IRQ2, the 'cascade', so to make it the highest priority, the first chip would have to be even higher-priority which, by definition, is impossible. Then, the SMP machines don't use these controllers at all unless the APIC is broken.
Cheers, Dick Johnson ***** FILE SYSTEM MODIFIED ***** Penguin : Linux version 2.1.108 on an i586 machine (66.15 BogoMips). Warning : It's hard to remain at the trailing edge of technology.
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