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SubjectRe: Thread implementations...
   Date: 	Sat, 20 Jun 1998 20:12:35 -0700
From: "David S. Miller" <davem@dm.cobaltmicro.com>

I assumed that TSS switches were defined to reload csr3, which by
definition flushes the TLB of user entires.

Thats broken, not because it's a silly workaround for the Intel TLB
mis-design, but rather because it changes behavior from what older
CPU's did. So if someone optimized things to defer TLB flushes for
mapping changes, when they knew they would task switch once before
running the task again, this "microcode optimization" would break the
behavior such a trick would depend upon.

Later,
David S. Miller
davem@dm.cobaltmicro.com

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