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SubjectRe: MMX based IP-checksumming patch, 2.1.105, RFC
[sent to linux-kernel and cc'd to cited author]

>>>>> "mingo" == mingo <> writes:

mingo> [...] I'm posting it here because maybe someone out there has ideas
mingo> how to prevent the quite expensive FPU_SAVE / RESTORE
mingo> operations somehow ... the routine itself basically clobbers
mingo> only 2 MMX registers.

mingo> [...] but for most RL MTU's the FPU save/restore operation eats
mingo> a considerable amount of the saved cycles ...

has this been tried on an AMD K6 yet? i thought they had a fast
MMX/FPU switch, an order of magnitude faster than the P5MMX. or is
this switch independent of the FPU save/restore times?

just a thought,

p.s. if you would like me to try this myself, i'll try to do so in the
next few days. i'm getting a k6-2 whenever i can convince the
UPS people to give it to me...
Tkil * <URL:> * hopelessly hopeless romantic.
"So amplify this little one | She hears as much as she can see
She's a volume freak | And what she sees, she can't believe."
-- Catherine Wheel, _Happy Days_, "Judy Staring At The Sun"

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