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    SubjectRe: cpu misdetection
    On Thu, 21 May 1998, Ragnar Hojland Espinosa wrote:

    > Correct output with previous kernels:
    > model : 6x86MX 2.5x Core/Bus Clock
    > [...]
    > Incorrect output with kernel 2.1.103:
    > model : Cx486SLC

    This is presumably because the Cyrix id stuff in head.S was
    disabled. Apparently it causes problems with some newer
    Intel chipsets which (accidentally?) use the same ports as
    Cyrix use for their CPU configuration. Without reading DIR0
    and DIR1 we don't know what the CPU is other than that it
    is a Cyrix of some kind - but probably a Cx486 since the
    early Cx486s didn't have the DIRx configuration ports.

    Incidentally does anyone know the actual circumstances the
    problem appears in? I've only seen vague posts that there is
    a problem here. You see we only touch ports 0x22 and 0x23 if
    the CPU behaves like a Cyrix in certain circumstances plus
    valid writes to 0x22 followed by access to 0x23 on a Cyrix
    should not generate external bus cycles. So either the Cyrix
    is generating external cycles in parallel with the internal
    configuration port access when it shouldn't or Intel have,
    ah, "emulated" the Cyrix behaviour we are testing for in
    order to trick us into I/O on 0x22, 0x23 when the CPU is
    not going to intercept them. (The misidentification would
    not be reported because the Intel chip would go on to
    respond to CPUID). If someone can shed light on what combinations
    of motherboard chipset and CPU have problems it may be possible
    to fix it rather than cripple it.

    Mike

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