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SubjectRe: Cyrix 6x86
> > Let's leave this choice to the Cyrix user. The CPU reports "have TSC", 
> > well, be it so, unless a kernel option says "suspend-on-halt".
> > The tiny Cyrix specific code to 1) clear the TSC capability flag 2) turn
> > on suspend-on-halt could probably go ...
>
> Couldn't this condition be detected dynamically by setting a timer
> interrupt, doing a halt, and then inspecting the TSC before and after?

Of course. I assume we have already detected this bug somehow.

However, someone may want to treat the TSC as reliable (consequently,
they will want to avoid the SOH), others may prefer having SOH
(consequently, they will have to avoid relying on their TSC except
for some specific safe uses).

Both choices seem reasonable and we are not forced to pick one, so I'd
probably make the choice a kernel option. I also think any generic
TSC use should not care about some random Cyrix chip at all, therefore
we should probably have the main TSC flag set differently depending
on that choice.

(We call the bug "TSC bug", but somebody might call it "SOH bug"
instead.)

Jirka


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