Messages in this thread | | | Date | Wed, 20 May 1998 00:47:19 -0600 (MDT) | From | james rich <> | Subject | Re: [PATCH-1] new apic irq-handling |
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I applied this patch to 2.1.102 cleanly, but some things are still strange. In the logs I keep getting:
spurious APIC interrupt, ayiee, should never happen.
but the system seems stable (up 24 hours now with the patch). /proc/interrupts is really strange though:
CPU0 CPU1 0: 8342725 4577 XT-PIC timer 1: 470 539 IO-APIC-edge keyboard 2: 0 0 XT-PIC cascade 4: 53987 61408 IO-APIC-edge serial 5: 1314 1578 IO-APIC-edge 3c509 8: 0 0 IO-APIC-edge rtc 12: 110963 129674 IO-APIC-edge PS/2 Mouse 13: 1 0 XT-PIC fpu 14: 6410 4949 IO-APIC-edge ide0 19: 37248 37180 IO-APIC-level BusLogic BT-958 NMI: 0 IPI: 0
I thought that XT-PIC interrupts could only be received on one processor. Why is timer on two? Why is timer an XT-PIC (it has always been this way)?
James Rich
james.rich@m.cc.utah.edu
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