Messages in this thread | | | From | (Alan Cox) | Subject | Re: Linux timekeeping plans | Date | Sun, 6 Dec 1998 19:46:57 +0000 (GMT) |
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> It seems that the steps that take place between the sender reading the > tsc and the receiver reading it are pretty well defined. How will this > not work?
They are well defined. Things like DMA and other memory bus activity perturb it but statistically they will be valid for x86
> This removes the need to spin waiting for signal_sent to be cleared, > since it's subsumed by the receive_ready spin.
Yep
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