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SubjectRe: The history of the Linux OS


On Thu, 26 Nov 1998, Brandon S. Allbery KF8NH wrote:

> In message <Pine.HPP.3.96.981126194004.966G-100000@gra-ux1.iram.es>, Gabriel
> Pa
> ubert writes:
> +-----
> | Even the first ISA bus had 20 address lines (although x86 I/O instructions
> | use only 16). Probably the reason to decode only 10 bits was rather that
> | the address decoder could be implemented in a simple 16 or 20 pin DIL chip
> | (PAL or whatever) on what was then an expansion board, because at the time
> | anything with more than 20 pins was huge and expensive.
> +--->8
>
> Interesting. The reference I've been using only shows 10; but then, it's
> hardly an official reference, and the source needs to be considered as well
> (something put out by Compute! magazine back in the mid 1980s). I already
> know the bloody thing was inaccurate about a number of other technical
> details.

No, all 20 bits were there (hint: the buffers that drive the ISA addresses
are directly on the processor address/bus, with another layer of buffers
on the MoBo taking these buffered signals to multiplex them into the DRAM
address pins).

And the ISA slots then could also be used to expand main memory with huge
boards holding as much as 256kB of DRAM ! What's interesting too is the
DRAM characteristic: 16 kbit chips with 250 nS access time and 410 nS
cycle time. DRAM capacities have increased tremendously (fortunately for
some companies who bloat SW for the sake of bloating it), improvements in
access/cycle times have been very relatively very slow.

However, even the decoder for onboard peripherals (DMA/Timer/8259/...)
"conveniently" forgets to decode more than 10 bits. Could have been done
cleanly with a single additional TTL chip...

Gabriel.


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