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SubjectRe: Non-page-aligned PCI base address


On Wed, 25 Nov 1998, Gabriel Paubert wrote:
**
**Yeah, but ioremap() on x86 fails when the physical address you request
to
**remap is not page-aligned. It doesn't on Sparc/Alpha and PPC AFAICT from
**a cursory reading of the code since all the PCI memory space is mapped.
**
**I consider this as both a bug and a feature :-):
**
**- the bug: PCI spcifications dor not require it,
**- the feature: if you use mmap to PCI space from user mode like X does,it
** is better to have at most one device per page, and in this case the
** device area can always be page aligned.
**
** Gabriel.
**

This sort of PCI base address assignement doesn't happen actualy often.
This was the first case known to me and it happend on kind of exotic
board. But maybe it could be considered that future x86 mainboards are
going to have more than 4 PCI slots on multiple buses and therefore such
'bug-feature' behaviour.

The problem solution I'm thinking about could be some re-assignment of PCI
base addresses during setup of pci_dev, in the similar manner it is donne
with PCI interrupts:

in pci.c:

1. check if the base address is page-aligned
2. if not, see if is it possible to align it and on success
write new base addr into base config
3. if the address is already used by other region, see if it is
possible to rearange other devices

Does it make any sense ?



**
**
**On Tue, 24 Nov 1998, Martin Mares wrote:
**
**> Hi,
**>
**> > Does anybody has an idea how to fix above ? I couldn't find anything about
**> > it in any docs/code. The box where my kernel module was tested (AMI
**> > Motherboard Goliath II PCI/EISA) has 7 PCI slots on 2 buses (that means,
**> > probably too much), and by some cards I got
**> >
**> > this strange base 0 addr: 0xfebffd80 (as found in pci_dev->base_address[0];
**> > ^^^
**> > The size of base0 is 0x80. Is it possible that bios makes some attempts
**> > to 'save' address space, being too pedantic ?
**> >
**> > This is bad if I want to perform ioremap() to access control registers of
**> > the card through mapped memory (needed in ISR for IRQ status/config regs
**> > access). The kernel where it was tested was 2.1.108. Momentary, I'm
**> > aligning the address to the nearest bottom page and ioremap it, keeping
**> > track of the address offset when accessing it. But is sucha thing realy
**> > necessary ?
**> >
**> > Please cc my address if you got some answer, as I'm not subscribed here.
**>
**> This seems to be perfectly correct -- PCI just states every memory / I/O
**> region has to be aligned to a multiple of its size and that the size is
**> a power of two >= 16 (memory) or 4 (I/O). Therefore you cannot expect
**> memory regions smaller than 4K to be page-aligned.
**>
**> Anyway, can you send me lspci -vvx output for this device?
**>
**



s.i.m.o.n.


___________v_/_________________________________________________________________
simon pogarcic sim@suse.de www.suse.de/~sim
_______________________________________________________________________________



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