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SubjectRe: Accessing MMIO PCI space - crossplatform (fwd)
	As requested.

---
'Cloning and the reprogramming of DNA is the first serious step in
becoming one with God.'
- Scientist G. Richard Seed

---------- Forwarded message ----------
Date: Fri, 13 Nov 1998 11:08:07 +0100 (MET)
From: Steffen Seeger <s.seeger@physik.tu-chemnitz.de>
To: ggi-develop@eskimo.com
Subject: Re: Accessing MMIO PCI space - crossplatform (fwd)

> This came from linux-kernel just now. We have been discussing
> some of the same issues....
>
> Jon

Jon, could you please respond to this email and propose our KGI IO regions
scheme as an *proposal* how to enhance the current read/write interface.

Please also forward any replies on linux-kernel to this list.
Thanks...

Steffen

----------------- e-mail: seeger@physik.tu-chemnitz.de -----------------
------------- The GGI Project: http://www.ggi-project.org --------------


/* ----------------------------------------------------------------------------
** hardware I/O layer definiton
** ----------------------------------------------------------------------------
**
** Copyright (C) 1997-1998 by Steffen Seeger
**
** ----------------------------------------------------------------------------
** MAINTAINER Steffen_Seeger
**
** $Log: io.h,v $
** Revision 1.2 1998/08/14 20:05:16 seeger_s
** - redefined IRQ interface.
**
** Revision 1.1 1998/07/19 22:54:17 seeger_s
** - implemented I/O functions
**
*/
#ifndef __ggi_io_h
#define __ggi_io_h

/* Explanations on I/O regions can be found in the system layer
** documentation.
*/

/* ----------------------------------------------------------------------------
** PCI configuration space
** ----------------------------------------------------------------------------
** These functions should be used to access the PCI configuration space.
** As the address is given by the hardware wiring, a registration
** scheme doesn't make sense. But I/O is pretty useful :) For the same
** reason, and as it is used for configuration (bootstrap) purposes,
** a physical->virtual mapping is not possible. All addresses are
** virtual and no mapping takes place.
*/
#ifdef __GGI_SYS_IO_HAS_PCICFG

#define PCICFG_NULL ((pcicfg_vaddr) -1) /* an invalid virtual address */

typedef __ggi_sys_u32 pcicfg_vaddr; /* the virtual address type */

#define PCICFG_VADDR(bus, slot, fn) \
((pcicfg_vaddr)((((bus) & 0xFF) << 24) | (PCI_DEVFN(slot,fn) << 16)))
#define PCICFG_BUS(vaddr) (((vaddr) >> 24) & 0xFF)
#define PCICFG_DEV(vaddr) PCI_SLOT(((vaddr) >> 16) & 0xFF)
#define PCICFG_FN(vaddr) PCI_FUNC(((vaddr) >> 16) & 0xFF)
#define PCICFG_REG(vaddr) ((vaddr) & 0xFFFF)
#define PCICFG_SIGNATURE(vendor, device) ((vendor << 16) | device)

extern int pcicfg_find(pcicfg_vaddr *addr, const __ggi_sys_u32 *signatures);

extern __ggi_sys_u8 pcicfg_in8 (const pcicfg_vaddr vaddr);
extern __ggi_sys_u16 pcicfg_in16(const pcicfg_vaddr vaddr);
extern __ggi_sys_u32 pcicfg_in32(const pcicfg_vaddr vaddr);

extern void pcicfg_out8 (const __ggi_sys_u8 val, const pcicfg_vaddr vaddr);
extern void pcicfg_out16(const __ggi_sys_u16 val, const pcicfg_vaddr vaddr);
extern void pcicfg_out32(const __ggi_sys_u32 val, const pcicfg_vaddr vaddr);

#endif /* #ifdef __GGI_SYS_IO_HAS_PCICFG */


/* ----------------------------------------------------------------------------
** Intel style in/out I/O space
** ----------------------------------------------------------------------------
** The io_in.. / io_out.. functions generate the neccesary hardware
** actions to do a read/write cycle in a cards I/O space. (Registers
** accessed via the in.. / out.. instructions on i386 architecture.)
*/
#ifdef __GGI_SYS_IO_HAS_IO

#define IO_NULL ((io_vaddr) 0) /* an invalid virtual address */
#define IO_DECODE_ALL ((io_addr) -1) /* all lines being decoded */

typedef unsigned int io_addr; /* the physical address type */
typedef unsigned int io_vaddr; /* the virtual address type */

struct io_region
{
pcicfg_vaddr device; /* (PCI) device this belongs to */
io_vaddr base_virt; /* virtual base address */
io_addr base_io; /* I/O base address */
io_addr base_bus; /* bus address */
io_addr base_phys; /* physical address */
io_addr size; /* size of region */
io_addr decode; /* decoded I/O address lines */
char *name; /* name of the region */
};

extern int io_check_region(struct io_region *r);
extern io_vaddr io_claim_region(struct io_region *r);
extern io_vaddr io_free_region(struct io_region *r);
extern io_vaddr io_alloc_region(struct io_region *r);

extern __ggi_sys_u8 io_in8 (const io_vaddr vaddr);
extern __ggi_sys_u16 io_in16(const io_vaddr vaddr);
extern __ggi_sys_u32 io_in32(const io_vaddr vaddr);

extern void io_out8 (const __ggi_sys_u8 val, const io_vaddr vaddr);
extern void io_out16(const __ggi_sys_u16 val, const io_vaddr vaddr);
extern void io_out32(const __ggi_sys_u32 val, const io_vaddr vaddr);

extern void io_ins8 (const io_vaddr addr, void *buf, unsigned long cnt);
extern void io_ins16(const io_vaddr addr, void *buf, unsigned long cnt);
extern void io_ins32(const io_vaddr addr, void *buf, unsigned long cnt);

extern void io_outs8 (const io_vaddr addr, const void *buf, unsigned long cnt);
extern void io_outs16(const io_vaddr addr, const void *buf, unsigned long cnt);
extern void io_outs32(const io_vaddr addr, const void *buf, unsigned long cnt);

#endif /* #ifdef __GGI_SYS_IO_HAS_IO */

/* ----------------------------------------------------------------------------
** memory I/O space
** ----------------------------------------------------------------------------
** This is the 'normal' shared memory I/O space accessed using the
** mov instructions on i386 architecture. The difference between
** *vaddr = val and mem_out32(val, vaddr) is that the latter will not
** be optimized away when compiling with maximum optimization.
*/
#ifdef __GGI_SYS_IO_HAS_MEM

#define MEM_NULL ((mem_vaddr) 0) /* an invalid virtual address */
#define MEM_DECODE_ALL ((mem_addr) -1) /* all lines being decoded */

typedef unsigned int mem_addr; /* the physical address type */
typedef void * mem_vaddr; /* the virtual address type */

struct mem_region
{
pcicfg_vaddr device; /* (PCI) device this belongs to */
mem_vaddr base_virt; /* virtual base address */
mem_addr base_io; /* the I/O base address */
mem_addr base_bus; /* bus address */
mem_addr base_phys; /* physical address */
mem_addr size; /* size of region */
mem_addr decode; /* decoded io address lines */
char *name; /* name of the region */
};

extern int mem_check_region(struct mem_region *r);
extern mem_vaddr mem_claim_region(struct mem_region *r);
extern mem_vaddr mem_free_region(struct mem_region *r);
extern mem_vaddr mem_alloc_region(struct mem_region *r);

extern __ggi_sys_u8 mem_in8 (const mem_vaddr vaddr);
extern __ggi_sys_u16 mem_in16(const mem_vaddr vaddr);
extern __ggi_sys_u32 mem_in32(const mem_vaddr vaddr);

extern void mem_out8 (const __ggi_sys_u8 val, const mem_vaddr vaddr);
extern void mem_out16(const __ggi_sys_u16 val, const mem_vaddr vaddr);
extern void mem_out32(const __ggi_sys_u32 val, const mem_vaddr vaddr);

extern void mem_ins8 (const mem_vaddr addr, void *buf, unsigned long cnt);
extern void mem_ins16(const mem_vaddr addr, void *buf, unsigned long cnt);
extern void mem_ins32(const mem_vaddr addr, void *buf, unsigned long cnt);

extern void mem_outs8 (const mem_vaddr addr, const void *buf,unsigned long cnt);
extern void mem_outs16(const mem_vaddr addr, const void *buf,unsigned long cnt);
extern void mem_outs32(const mem_vaddr addr, const void *buf,unsigned long cnt);

#endif /* #ifdef GGI_SYS_IO_HAS_MEM */

/* ----------------------------------------------------------------------------
** irq handling
** ----------------------------------------------------------------------------
** use similar to io regions.
*/
#ifdef __GGI_SYS_IO_HAS_IRQ

#define IRQ_NULL ((unsigned int) -1) /* an invalid irq line */
#define IRQ_DECODE_ALL ((irq_mask) -1) /* all lines being decoded */

typedef unsigned int irq_mask;

enum irq_flags
{
IF_SHARED_IRQ = 0x00000001

};

struct irq_line
{
enum irq_flags flags; /* properties */
char *name; /* name of the line */
unsigned int line; /* requested IRQ line */

void *high_priv; /* high priority handler priv. */
int (*High)(void *priv, void *regs); /* high priority handler */

void *low_priv; /* low priority handler private */
void (*Low)(void *priv); /* low priority handler, improve!!! */
};

/* These may be OS dependent, and have to be supplied by the OS/kernel
** layer. As they aren't performance critical either, a call doesn't hurt.
*/
extern int irq_claim_line(struct irq_line *irq);
extern void irq_free_line(struct irq_line *irq);

#endif /* #ifdef __GGI_SYS_IO_HAS_IRQ */

#undef __GGI_SYS_IO_HAS_PCICFG
#undef __GGI_SYS_IO_HAS_IO
#undef __GGI_SYS_IO_HAS_MEM
#undef __GGI_SYS_IO_HAS_IRQ

#endif /* #ifdef __ggi_io_h */



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