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SubjectRe: cat /proc/pci and NCR 810 SCSI parity error

On Wed, 7 Oct 1998, Gabriel Paubert wrote:

> On Wed, 7 Oct 1998, Harald Koenig wrote:
>
> > using 2.1.122 with CONFIG_PCI_OLD_PROC=y I get a SCSI parity error
> > when running
> >
> > # od -tx1 -Ax /proc/bus/pci/00/01.0
> > # cat /proc/pci
> >
> > where /proc/bus/pci/00/01.0 is the NCR810 (kernel messages below)
> >
> >
> > any idea what's wrong with accessing /proc/bus/pci/00/01.0 and `cat /proc/pci'
> > and/or 2.1.122 ?
> >
>
> I have the same effect when doing the same operation on a 53C825A.

For the same reason Harald got it.

> However it only occurs when typing the od command from a root account. So
> it's a non issue (only root can provoke it and it does not seem to do any
> harm), it might even be (highly speculative, I don't have the docs) that a
> feature of the chip is the ability to inject artificial parity errors for
> testing, although it would be weird to do it from read access of the
> configuration space.

It has such a feature that is useless the way it is designed, IMO.
I have sent my explantion of this problem in my reply to Harald.

> Note that typing lspci -xx whill have exactly the same effect as od, only
> that not everybody making the transition from 2.0.xx to 2.1.xx has
> downloaded pciutils.
>
> Some Intel chipsets lockup when reading the whole configuration space
> AFAIR: using od or lspci -xx on /proc/bus/pci/... is not always safe from
> a root account. From non root accounts, you can only read the first 64
> bytes of config space, which has been safe on all devices until now, but
> cannot even been guaranteed in the future given the general tendency to
> violate PCI specs in new and innovative ways :-) These violations are
> often due to little known companies like Intel, Compaq, S3, etc... who
> carefully target their R&D resources to keep up with their reputation for
> being innovative :-)

PCI specs require device to support 256 byte of config space, 64 bytes
for the predefined header and the rest being device specific.
If the PCI specs say that the device specific region can be read without
any side effects, then these devices are not PCI compliant. Does they?

PCI specifications violations are quite common not only from hardware.
Sometimes you are required to do so from a device driver in order to work
around chip bugs, sometimes you just want your driver or hardware to be
faster.

I am wondering about PCI systems working so well and being so much
violated at the same time. :-)

Regards,
Gerard.


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